The present invention relates generally to integrated circuit designs, and more particularly to methods for implementing averaging flash analog signal to digital signal converters (ADCs) that utilize shared capacitor networks.
Analog-to-Digital converters (ADC) have been in use in various engineering solutions, and are keys to the quality and speed of many electronic systems. Various analog-to-digital conversion techniques exist, and they vary in complexity and speed of conversion. Some of these techniques are sigma-delta ADC and pipeline ADC. One of the fastest and most commonly used types of ADC is the “FLASH” ADC. It utilizes comparators to compare the input signal level with each of the possible quantization levels. The outputs of the comparators are processed by an encoding logic block to provide the number of bits of the output digital word. An example of a flash ADC such as an averaging flash ADC, uses ratio-capacitor networks to average the coarse comparator output for a second step second stage comparison. Such a flash ADC has many advantages. A flash ADC has a high bandwidth, little intrinsic delays, and is relatively easy to design, and can perform fast analog-to-digital conversions. With flash ADC, a complete conversion can be obtained within one clock cycle.
However, conventional circuit designs of flash ADC such as an averaging flash ADC are typically composed of large component counts leading to large physical size. For example, a conventional 8-bit averaging flash ADC uses a 2^N method to determine the number of ratio-capacitors and second stage comparators used for an N-bit ADC. For a simple 8-bit ADC, 256 ratio-capacitors and 256 second stage comparators will be required which take up a large amount of space. The high number of components and large physical size can also create problems such as higher power consumption and production cost. The large number of comparators can also add a huge capacitive load to the analog input signal, thereby limiting the input signal bandwidth.
It is therefore desirable to have an improved flash ADC circuit design that can reduce component counts and physical size of the circuit.